Issue No.01 - January-February (2008 vol.25)
John Mark Nolen , Texas A&M University
Rabi N. Mahapatra , Texas A&M University
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.27
Much current research has focused on employing networks on chips (NoCs) for communication among numerous cores on large-scale SoCs. One side benefit of such designs is the potential to use this communication infrastructure with little modification for manufacturing test delivery. This article presents a test-scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower-rate test execution at the target cores. To achieve this, the authors interleave test data over the network via time-division multiplexing (TDM). To demonstrate the utility of this approach, they present a test-scheduling algorithm and a simulated test case from ITC 2002 SoC benchmarks. The results show significant test time and I/O savings when compared to a single-clock approach.
embedded-core testing, SoC, NoC, test access mechanism, TAM, scan test delivery, time-division multiplexing, TDM
John Mark Nolen, Rabi N. Mahapatra, "Time-Division-Multiplexed Test Delivery for NoC Systems", IEEE Design & Test of Computers, vol.25, no. 1, pp. 44-51, January-February 2008, doi:10.1109/MDT.2008.27