Issue No. 01 - January-February (2008 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.7
Yves Joannon , Grenoble Institute of Technology
Vincent Beroulle , Grenoble Institute of Technology
Chantal Robach , Grenoble Institute of Technology
Smail Tedjini , Grenoble Institute of Technology
Jean-Louis Carbonéro , STMicroelectronics
The test cost of heterogeneous ICs has significantly increased. So, the definition of relevant test methods and efficient test stimuli are becoming critical research orientations for semiconductor manufacturers. The authors of this article propose decreasing the manufacturing test cost of analog and mixed-signal (AMS) and RF SoCs by automatically qualifying and optimizing the existing test set. Their computer-aided test (CAT) tool, Plasma, uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. After discussing the advantages using behavioral fault models, the authors present a method that lets them decrease overall simulation time. This method reduces the number of simulated fault-free models, thanks to a normal estimation.
fault-based test, qualification, design validation, AMS and RF SoCs, VHDL-AMS, behavioral modeling, parametric fault injection
S. Tedjini, Y. Joannon, V. Beroulle, C. Robach and J. Carbonéro, "Decreasing Test Qualification Time in AMS and RF Systems," in IEEE Design & Test of Computers, vol. 25, no. , pp. 29-37, 2008.