Issue No. 01 - January-February (2008 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.13
Craig Force , Texas Instruments
Bruce C. Kim , University of Alabama
There are several challenges facing RFIC design and test. The demand in the wireless market will drive RFIC products. For RFIC chipsets, improvements are needed for the elimination of passive components, better integrated passives, power reduction, modeling of devices and interconnects, packaging, and cost-effective testing. However, this innovation cannot come at the cost of time to market for new products. Also, development costs must be driven to a minimum, as average selling prices for RFICs remain flat or decline. Moreover, one of the biggest challenges in moving from low GHz to higher frequencies is the lack of integration between the production testing infrastructure, EDA tools, and device designs. Advancements in device and test equipment modeling and simulation technology are beginning to bridge this gap. Finally, RF measurement requires specialized capital equipment investments and highly skilled engineers with many years of experience. This special issue on design and test of RFIC chips describes some of these challenges and proposes some interesting solutions.
RFIC chips, RF measurement, CMOS technology, wireless, design and test
Craig Force, Bruce C. Kim, "Guest Editors' Introduction: The Evolution of RFIC Design and Test", IEEE Design & Test of Computers, vol. 25, no. , pp. 6-8, January-February 2008, doi:10.1109/MDT.2008.13