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Issue No. 06 - November-December (2007 vol. 24)
ISSN: 0740-7475
pp: 546-555
Sylvain Guilley , École Nationale Supérieure des Télécommunications
Florent Flament , Hewlett-Packard
Philippe Hoogvorst , Centre National de la Recherche Scientifique
Renaud Pacalet , École Nationale Supérieure des Télécommunications
Yves Mathieu , École Nationale Supérieure des Télécommunications
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a fully custom-balanced cell library and an innovative place-and-route method. This article shows that it is indeed possible to implement hardware that is robust against all known power attacks. All the design steps involved in this methodology take place at the layout level. The described flow has been applied to the quasi-delay-insensitive SecLib library with a shielded routing method derived from back-end duplication, using legacy CAD tools for the back-end steps. The authors evaluate the cost of the secured methodology through an example of a multimode DES datapath.
robust hardware, back-end design automation, power-constant architectures, side-channel attacks, mitigation, DFM, DFY

Y. Mathieu, R. Pacalet, F. Flament, P. Hoogvorst and S. Guilley, "Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors," in IEEE Design & Test of Computers, vol. 24, no. , pp. 546-555, 2007.
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