Issue No. 05 - September-October (2007 vol. 24)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.177
Jerzy Tyszer , Poznań University of Technology
Janusz Rajski , Mentor Graphics
Grzegorz Mrugalski , Mentor Graphics
Nilanjan Mukherjee , Mentor Graphics
Mark Kassab , Mentor Graphics
Wu-Tung Cheng , Mentor Graphics
Manish Sharma , Mentor Graphics
Liyang Lai , Mentor Graphics
This article presents a two-stage test response compactor with scan selection logic and an on-chip compare-and-response collector. This compactor is capable of handling a wide range of X state profiles, offers compression far higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution.
DFT, embedded test, fault diagnosis, on-chip collection of test data, scan-based designs, selective compaction of test responses
M. Kassab et al., "X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis," in IEEE Design & Test of Computers, vol. 24, no. , pp. 476-485, 2007.