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Issue No. 05 - September-October (2007 vol. 24)
ISSN: 0740-7475
pp: 430-441
Miloš Krstić , IHP Microelectronics
Eckhard Grass , IHP Microelectronics
Frank K. Gürkaynak , Swiss Federal Institute of Technology Lausanne
Pascal Vivet , CEA-LETI
For more than 20 years, significant research effort was concentrated on globally asynchronous, locally synchronous (GALS) design methodologies. But despite several successful implementations, GALS has had little impact on industry products. This article presents different GALS techniques and architectures. The authors also analyze the actual challenges and problems for wider adoption of the currently proposed GALS methods. Their analysis shows that significant improvement can be achieved in terms of system integration and EMI reduction. On the other hand, for power savings, only marginal improvements to the existing techniques can be expected. Additionally, introduction of a GALS approach leads to relatively small area increases, and in some cases even causes certain performance losses. The authors present major examples of GALS implementations. Finally, they outline some directions for future development of GALS techniques and their design flow. It is quite clear that the GALS design and test flow must be improved and more automated. Furthermore, the attendant performance degradations must be limited--for example, high data throughput must be ensured through very low hardware overhead for the GALS circuitry.
VLSI, asynchronous/synchronous operation, interfaces, GALS

P. Vivet, M. Krstić, F. K. Gürkaynak and E. Grass, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook," in IEEE Design & Test of Computers, vol. 24, no. , pp. 430-441, 2007.
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