Issue No. 04 - July/August (2007 vol. 24)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.148
V.R. Devanathan , Texas Instruments India
V. Kamakoti , Indian Institute of Technology, Madras
C.P. Ravikumar , Texas Instruments India
Modern SoC devices use elaborate power management strategies in functional mode, because not all IP blocks can be functional at the same time. Cost considerations often do not permit overdesigning the power supply infrastructure for test mode or using expensive flip-chip packaging to avoid the problem. Test application must not overexercise the power supply grids, lest the tests damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. The problem is aggravated by on-chip variations in technologies below 100 nm. However, it's possible to avoid false delay test failures by generating safe patterns that are tolerant to on-chip variations. The authors propose a framework for power-safe pattern generation that uses power grid information and regional constraints on switching activity. Experimental results with benchmark circuits demonstrate the effectiveness of this framework.
low-power ATPG, peak power, IR drop, power profiling, process variation
V.R. Devanathan, V. Kamakoti, C.P. Ravikumar, "Variation-Tolerant, Power-Safe Pattern Generation", IEEE Design & Test of Computers, vol. 24, no. , pp. 374-384, July/August 2007, doi:10.1109/MDT.2007.148