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Issue No. 04 - July/August (2007 vol. 24)
ISSN: 0740-7475
pp: 312-321
Smita Krishnaswamy , University of Michigan
Igor L. Markov , University of Michigan
John P. Hayes , University of Michigan
Probabilistic faults are increasingly affecting logic circuits in the nanometer realm. Examples include transients caused by cosmic radiation, randomness in quantum and nanocircuits, and process variability in manufacturing. The authors of this article generalize the variations caused by these faults to the notion of a probabilistic fault model. They then delineate the differences between these faults and the more traditional deterministic faults. Such effects require a reformulation of testing and test-generation methods. In particular, the same fault can be detected by several test vectors, with varying probabilities. The authors call the probability that a test vector detects a fault its "sensitivity" to the fault. They propose test generation methods for probabilistic faults with the goal of bounding and estimating fault probabilities. Finally, the authors propose a fault-modeling framework for efficient representation of probabilistic faults, algorithms to compute test-vector sensitivity, and integer linear programming (ILP) to generate compact test sets with high probabilities of coverage.
probabilistic faults, logic circuit testing, integer linear programming, fault-modeling framework, test-vector sensitivity

J. P. Hayes, I. L. Markov and S. Krishnaswamy, "Tracking Uncertainty with Probabilistic Logic Circuit Testing," in IEEE Design & Test of Computers, vol. 24, no. , pp. 312-321, 2007.
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