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Guest Editors' Introduction: The State of the Art in Nanoscale CAD

Fabrizio Lombardi, Northeastern University
Cecilia Metra, University of Bologna

Pages: pp. 302-303

It is with great pleasure that we introduce this Special Section on Computer-Aided Design for Emerging Technologies to the readers of IEEE Design & Test. This special section consists of three articles that cover a spectrum of techniques encountered in computer-aided design of devices, circuits, and systems using emerging technologies. These articles are authored by outstanding researchers, and they cover both experimental and speculative topics. Of course, as with any special section, these topics are only representative of the available literature currently provided by the technical community.

Because of very small feature size (based on molecular- and atomic-level devices), high integration levels, and innovative computational features, new concerns are emerging regarding the implementation of computing systems, leading to increased interest in nanoscale technology. Continued scaling of current top-down trends suggests the need for features measured in the nanometer range to meet the objectives of the International Technology Roadmap for Semiconductors ( ITRS) over the next few decades. As new techniques to synthesize nanostructures from the bottom up emerge to expand device options and design space, there is considerable evidence that design practice will require CAD as a framework.

Moreover, new tools are necessary for VLSI so that designers can assess the different capabilities for assembling devices into circuits and systems. To properly understand and exploit nanoscale technologies, a significant change is needed from the methodologies that have been adequate for today's submicron scales. The design of nanoscale systems is inherently complex and must consider phenomena such as statistical and probabilistic behavior, as well as reduction of parasitic effects. The challenge is to develop adequate engineering techniques, approaches, and design disciplines to tame and harness the capabilities that such a reduced scale may offer. Tools are a necessity to ensure that emerging technologies will move into industry for full commercialization. It is the convergence of all of these issues that will make CAD at the nanoscale level a vibrant, challenging topic for many years to come. This special section presents a timely account of the state of the art in this area, with emphasis on tools and related frameworks.

The first article, "An Overview of Nanoscale Devices and Circuits," by Jing Huang, Mariam Momenzadeh, and Fabrizio Lombardi, presents a detailed treatment of state-of-the-art advances in emerging technologies. Devices and circuits are outlined, with particular emphasis on current developments and future research directions. This article presents the principles by which different emerging technologies operate, as well as the manufacturing and modeling implications of these principles. In addition, this article highlights the practical viability of meeting some of the metrics that will be encountered at the end of the technology roadmap.

In the second article, "Tracking Uncertainty with Probabilistic Logic Circuit Testing," Smita Krishnaswamy, Igor Markov, and John Hayes present a novel general framework for analyzing probabilistic faults. Based on a fault-modeling generalization, this framework characterizes the disparate effects caused by probabilistic faults due to transients, as well as randomness for quantum effects and process variability in manufacturing. This is radically different from a traditional deterministic process—based on the stuck-at-fault model, for example. This framework provides an innovative reformulation of testing and can serve to design new tools for ATPG. The authors provide an efficient mathematical approach that relies on a multiset of test patterns (that is, with repetitions) to accomplish the likelihood of detection, or sensitivity.

The third article, "Leakage Minimization Technique for Nanoscale CMOS VLSI," by Kyung Ki Kim et al., describes a heuristic technique that establishes input values for reducing (and, in most cases, minimizing) leakage current in nanoscale CMOS circuits (such as at the 45-nm feature size). The heuristic nature of this approach is evident from the practical concerns the authors express in identifying an extensive array of possible causes that may generate leakage during standby mode. The authors use a macromodel to assess stack and fan-out effects.

We sincerely hope& that this special section will be a valuable reference for future research. The topics covered here are timely and important, and the authors have done an excellent job of presenting the material. We extend our sincere thanks to all the authors and reviewers. We also thank EIC Tim Cheng for allowing us to pursue this special section. Finally, we express our appreciation to all those who have helped in editing and assembling this special section. Please feel free to contact us if you have any questions or comments.

About the Authors

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Fabrizio Lombardi holds the International Test Conference Endowed Chair Professorship at Northeastern University, Boston. His research interests include CAD, VLSI testing, and defect tolerance. Lombardi has a BSc in electronic engineering from the University of Essex, Colchester, England; as well as an MSc in microwaves and modern optics, a diploma in microwave engineering, and a PhD in engineering, all from the University of London. He is the editor in chief of IEEE Transactions on Computers, an associate editor of IEEE Design & Test, and a member of the IEEE Computer Society.
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Cecilia Metra is an associate professor in the Department of Electronics, Computer Science, and Systems (DEIS) at the University of Bologna, Italy. She is also affiliated with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES) there. Her research interests include design and test of digital systems, reliable and error-resilient systems, fault tolerance, online testing, fault modeling, concurrent diagnosis, and debugging. Metra has a Laurea in electronic engineering and a PhD degree in electronic engineering and computer science from the University of Bologna. She is associate editor in chief of IEEE Transactions on Computers and a Golden Core Member of the IEEE Computer Society.
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