Issue No. 04 - July/August (2007 vol. 24)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.133
Cecilia Metra , University of Bologna
Fabrizio Lombardi , Northeastern University
Because of very small feature size, high integration levels, and innovative computational features, new concerns are emerging regarding the implementation of computing systems, leading to increased interest in nanoscale technology. Continued scaling of current top-down trends suggests the need for features measured in the nanometer range. As new techniques to synthesize nanostructures from the bottom up emerge, design practice will require CAD as a framework. Moreover, new tools are necessary for VLSI so that designers can assess the different capabilities for assembling devices into circuits and systems. The design of nanoscale systems is inherently complex and must consider phenomena such as statistical and probabilistic behavior, as well as reduction of parasitic effects. Tools are a necessity to ensure that emerging technologies will move into industry for full commercialization. The convergence of such issues will make CAD at the nanoscale level a vibrant, challenging topic for many years to come. This special section presents a timely account of the state of the art in this area, with emphasis on tools and related frameworks.
nanotechnology, CAD, feature size, nanostructures, VLSI
Cecilia Metra, Fabrizio Lombardi, "Guest Editors' Introduction: The State of the Art in Nanoscale CAD", IEEE Design & Test of Computers, vol. 24, no. , pp. 302-303, July/August 2007, doi:10.1109/MDT.2007.133