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Issue No. 04 - July/August (2007 vol. 24)
ISSN: 0740-7475
pp: 300
Recent innovations in nanoscale devices offer the potential for greater information density and system functionality. However, such devices present several new challenges. Design methodologies and tools have obtained a tremendous degree of sophistication and predictive value, and there are advantages in using the power of these tools to define a context for evaluating next-generation nanoelectronic technologies. Without a common context of systems evaluation, it will be difficult to make early viability assessments of new nanoelectronic-device approaches, nor will it be possible to strategically guide the development of these new technologies. This issue of IEEE Design & Test offers a special section on such topics. In addition, this issue presents the first in a series of tutorial articles derived from presentations at Test Technology Educational Program (TTEP) conferences. Finally, there are five general-interest articles on a wide range of topics.
CAD, CMOS, SEU, delay testing, process diagnosis, redundancy

T. Cheng, "Design and CAD for Nanotechnologies," in IEEE Design & Test of Computers, vol. 24, no. , pp. 300, 2007.
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