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Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs

Mohammad Tehranipoor, University of Connecticut
Kenneth M. Butler, Texas Instruments

Pages: pp. 214-215

As technology scales to 22 nm and functional density continues to rise, many factors and parameters have a direct impact on the design and test of chips. Among such challenges, IR-drop and power supply noise (PSN) effects have become more significant in recent years. Design and test engineers need to efficiently handle these effects because they can cause design, test, and reliability issues for the chip. Timing closure and functional verification cannot be considered complete until pre- and post-layout IR-drop, ground-bounce, and PSN effects have been estimated and the appropriate margins applied. These effects have complex interdependencies, and conventional design tools aren't capable of considering all of these effects and their interrelationships concurrently. Today's design and test engineers must deal with many issues, including the following:

  • IR-drop effects on path delay test,
  • IR-drop effects during faster-than-at-speed test,
  • power management during launch and capture of at-speed test,
  • fast and accurate IR-drop and PSN measurement,
  • pattern generation for worst-case IR-drop and PSN,
  • IR-drop and PSN-aware timing verification, and
  • library characterization for IR-drop-aware performance verification.

These challenges can necessitate advanced, potentially expensive solutions such as on-chip monitoring of PSN, power grid verification to ensure target chip performance, power and timing closure in the presence of IR drop and PSN, full-chip hot-spot identification, decoupling-capacitance allocation and optimization for PSN suppression, and new packaging methods.

This special issue addresses some of these issues, focusing on the impact of PSN on design and test of very deep-submicron designs and highlighting the importance of PSN and IR drop to design and test engineers in the semiconductor industry and researchers in academia. We received a surprisingly large number of high-quality articles, but we could include only a few in this special issue. The depth and breadth of response confirms that IR drop and PSN are gaining more attention from researchers in academia and industry.

The first article, "A Production IR-Drop Screen on a Chip," by Zahi Abuhamdeh et al., argues that IR drop can be very problematic because power rails might not be sized correctly for the load they must handle in both functional and test operation. So, there could be isolated hot spots or conditions of overtesting or test escapes. The authors describe a methodology that employs an on-chip process-monitoring circuit that is easy to integrate on chip and use in a characterization or production environment, to help identify and localize IR-drop hot spots and power-related failures.

The second article, "Modeling Power Supply Noise in Delay Testing," by Jing Wang, Duncan Walker, and Xiang Lu, addresses noise-induced overkill. The authors have developed two models for supply noise in delay testing, and they show how to apply these models in test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing PSN analysis tools.

In "Power Supply Noise in SoCs: Metrics, Management, and Measurement," Karim Arabi, Resve Saleh, and Xiongfei Meng argue that existing design and analysis techniques and metrics fail to provide an accurate impact estimation of PSN, making it difficult to optimize design and test procedures. This lack of predictability complicates timing closure, physical design, production test, and speed grading of SoCs. The authors describe and validate two metrics that quantify the impact of PSN. They propose using modified decoupling-capacitor designs, and they present results of silicon experimentation. Moreover, they address the true impact of PSN on production test and present DFT techniques to reduce PSN during test.

Next, "Power Grid Physics and Implications for CAD," by Sanjay Pant, Eli Chiprout, and David Blaauw, analyzes supply noise in a power distribution network to ensure reliable performance in high-performance designs. The authors describe a detailed, full-die dynamic model of an Intel Pentium IV microprocessor design. They justify this model from the bottom up, using a full-wave model and then increasingly larger but less detailed models with only the irrelevant elements removed at each step. They show that on-die inductance has minimal impact in such a design, and that package-die cosimulation is critical to understanding the resonant properties of the grid.

The fifth article, "Analysis of Power Supply Noise in the Presence of Process Variations," by Praveen Ghanta and Sarma Vrudhula, demonstrates that variability in the physical and electrical characteristics of ultra small devices and metal wires due to variations in the manufacturing process significantly impacts the performance of today's VLSI circuits. Characterizing the impact of variability on circuit performance characteristics such as delay, power, and signal integrity is inevitable to avoid chip failure. The authors present a comprehensive methodology for analyzing the impact of device and metal variations on the PSN, and hence the signal integrity of on-chip power grids.

"Scan-Based Tests with Low Switching Activity," by Santiago Remersaro et al., addresses the issue of excessive supply current and power dissipation during scan-based test. Greater-than-normal switching activity can occur during scan shifts and test response capture. Higher peak-current demands can lead to supply voltage droops, causing good chips to fail at-speed tests. Higher average-switching activity increases power dissipation and chip temperatures, leading to hot spots that can damage the circuits under test. The authors propose a method to derive tests with reduced switching activity during both scan shifts and test response capture.

Finally, "Power Droop Testing," by Ilia Polian et al., addresses the issue of testing power supply fluctuations. The authors propose a heuristic method to generate test sequences that create worst-case power drop by accumulating the high-frequency and low-frequency effects. The generated patterns must be sequential, even for scan designs.

We sincerely hope you enjoy this special issue, and we'd like to thank all the authors and reviewers for their tremendous efforts in producing these high-quality papers. We'd also like to take this opportunity to thank EIC Tim Cheng and the entire editorial staff of IEEE Design & Test for their encouragement and assistance in producing this special issue.

About the Authors

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Mohammad Tehranipoor is an assistant professor in the Department of Electrical and Computer Engineering at the University of Connecticut. His research interests include CAD and test for nanometer technology designs, DFT, at-speed test, and secure design. Tehranipoor has a BSc from Amirkabir University of Technology, an MSc from the University of Tehran, and a PhD from the University of Texas at Dallas, all in electrical engineering. He is a member of the IEEE Computer Society, the ACM, and ACM SIGDA.
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Kenneth M. Butler is a TI Fellow at Texas Instruments in Dallas, Texas. His research interests include outlier techniques for quality and reliability, and test-data-driven decision-making. Butler has a BS from Oklahoma State University, and an MS and a PhD from the University of Texas at Austin, all in electrical engineering. He is a senior member of the IEEE and a member of the ACM.
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