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Issue No. 03 - May-June (2007 vol. 24)
ISSN: 0740-7475
pp: 226-234
Jing Wang , Texas A&M Univ., College Station
D.M. Walker , Texas A&M Univ., College Station
ABSTRACT
Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and
INDEX TERMS
Power supplies, Delay, Circuit testing, Semiconductor device noise, Circuit noise, Noise generators, Voltage, CMOS technology, Noise reduction, Compaction,filling, delay test, power supply noise model, compaction
CITATION
Jing Wang, D.M. Walker, Xiang Lu, A. Majhi, B. Kruseman, G. Gronthoud, L.E. Villagra, P.J.A. van de Wiel, S. Eichenberger, "Modeling Power Supply Noise in Delay Testing", IEEE Design & Test of Computers, vol. 24, no. , pp. 226-234, May-June 2007, doi:10.1109/MDT.2007.76
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