, Sun Microsystems
Pages: pp. 198-199
Abstract—Reviewed in this issue
VLSI Test Principles and Architectures, edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, is partly a textbook and partly a collection of survey articles on testing by top experts. It works reasonably well in both contexts. Its target audience, according to the preface, includes both students and practitioners. Although this is a noble objective, I don't think any book can achieve it, and this book does not.
Before considering each chapter, I'd like to make some general comments. On the negative side, for its suitability as a textbook, it is unfortunate that only some of the chapters (usually those written by the editors) refer to other chapters, even when this would shorten the text. For example, the text on ATPG (chapter 4) does not refer back to the discussion on controllability and observability measures in chapter 2. On the plus side, there are many diagrams, all of high quality, and this helps make the concepts and test methods easy to understand.
The first chapter introduces the basic concepts of testing. It explains where testing fits into the design and manufacturing process, describes fault models, and briefly summarizes the different types of test.
The next chapter, entitled "Design for Testability," is process oriented, which I found to be appropriate for this subject. It begins with testability analysis, then moves to the design of scan cells, scan architectures, and the scan design flow. This chapter is complete, and very useful for someone trying to understand what DFT tools do.
Chapter 3 covers logic and fault simulation. Topics include basic algorithms, as well as nonsimulation methods such as statistical fault analysis, toggle coverage, and sampling. The amount of space given to each topic is commensurate with its importance. This is a good survey for the student or the few practitioners who use fault simulation outside the context of combinational ATPG or BIST.
The chapter on test generation (chapter 4) seems targeted to students. After a section on combinational test generation, with useful pseudocode for the major algorithms, there is a short section on sequential ATPG, then over 20 pages on simulation-based ATPGs. I found this excessive because, with full scan being vital for both practical test generation and circuit bring-up and debugging, I don't expect ATPG methods not based on scan to ever be useful to the practitioner.
The next chapter, on BIST, also spends a considerable amount of time on an area of limited interest—in this case, pseudo-exhaustive BIST. However, most of the chapter describes BIST architectures, which will be of great utility to the practitioner in understanding the operation of BIST tools. The section in this chapter on design rules is also useful, giving an outline of what rules are needed and why.
Chapter 6 is a survey on test compression. For the student, it covers both stimulus and response compression, outlining the major schemes. For the practitioner, the chapter concludes with descriptions of most of the major commercial solutions, written by experts from the companies selling them. These descriptions focus on the technical contributions of the techniques and are written at a level in which they will not become obsolete for at least a few years. This innovative chapter showcases a valuable new method of getting immediately useful information into a book on test.
The next chapter, on logic diagnosis, describes how to find the source of IC failures. Especially useful is a section on how to diagnose scan chain failures. Today's designs can hardly be debugged without scan, so getting the scan chain to work is usually the first order of business. The only thing missing here is a discussion on how to debug nonlogical faults, which are the nastiest type—but I doubt there is much theory yet on this subject.
Every text on DFT needs a chapter on memory test. The one here (chapter 8) covers some of the major memory test algorithms, then goes into detail on a memory fault simulator and a BIST generator from the university of this chapter's author. This is accomplished using an extensive example, but the detail is perhaps greater than needed. Although the research topics discussed here are very interesting, I think they will be of little use to the practitioner or student without access to the software described. The next chapter, on memory diagnosis and built-in self-repair, has the same issues: There is a detailed example, but the chapter is not very broad. For example, this chapter hardly touches on the essential technique of bit-mapping.
Chapter 9, "Boundary Scan and Core-Based Testing," is really on standards—specifically, IEEE 1149.1, IEEE 1149.6, and the new IEEE 1500 standard. As a tutorial, this chapter is clear, concise, and at the proper level for both student and practitioner. The chapter on analog and mixed-signal testing (chapter 10), also contains information on standards: IEEE 1057 on Digitizing Waveform Recorders and IEEE 1149.4 on Analog Boundary Scan. Much of this chapter is structured as bullet paragraphs, which worked well for me. Various analog test methods are described, and the information is tied to the real world by the inclusion of actual data sheets.
The final chapter (chapter 11) is entitled "Test Technology Trends in the Nanometer Age." You might expect this to be a summary chapter; but instead it contains sections on delay test, soft errors and defect-based test, FPGA test, and I/O test. Some of these sections—for instance, the one on I/O test—are quite good, but the chapter should be better titled.
The strengths of this book are the practical aspects discussed in many of its chapters, the good examples, and the depth of several chapters. The weaknesses are a lack of consistency of target audience across chapters and a lack of cohesiveness. The chapter on compression (chapter 6) is the best overview I've yet seen on the topic. Nearly everyone will get something out of this book, but prospective purchasers should review the topics of interest to see if the level is right for them.