Issue No. 02 - March-April (2007 vol. 24)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.41
Chao-Hsun Chen , National Tsing Hua University
Rei-Fu Huang , Media Tek
Cheng-Wen Wu , National Tsing Hua University
The demand for built-in self-repair (BISR) methodologies that improve the yield of embedded memories is growing. A typical BISR scheme requires circuit modules that perform built-in self-test (BIST), built-in redundancy analysis (BIRA), real-time address remapping, and so on. The objective of BISR design is to maximize the final yield while keeping a reasonably low hardware overhead. In this work, the authors propose cost and benefit models, and evaluate the economic effectiveness of typical memory BISR implementations. They also present a simulator for that purpose based on the proposed cost models. The results are useful for evaluating the BISR schemes and implementations. Experimental results show that memory size impacts the cost-effectiveness of BISR more than production volume does.
built-in self-repair, BISR, economic models, BIST, BIRA, redundancy analysis, yield, overhead
Chao-Hsun Chen, Rei-Fu Huang, Cheng-Wen Wu, "Economic Aspects of Memory Built-in Self-Repair", IEEE Design & Test of Computers, vol. 24, no. , pp. 164-172, March-April 2007, doi:10.1109/MDT.2007.41