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Functional verification remains a major bottleneck of the design process. Despite tremendous advances in both formal and simulation-based approaches, functional-verification technology still cannot keep pace with the rapid increases that have taken place in design complexity. The number of presilicon logic bugs has consistently increased for each new design generation. One logical approach to combating this verification bottleneck is to combine multiple, complementary techniques so that their combined strength is superior to the sum of the individual techniques. In this issue, we examine recent progress in this direction. Our guest editors—Jayanta Bhadra, Magdy Abadir, and Li-C. Wang (in collaboration with their colleague, Sandip Ray)—have contributed a comprehensive survey article on this subject and have selected four additional articles that demonstrate different ways to use this cocktail approach to achieve higher verification coverage and lower computational time.
In addition to these special-issue articles, you will also find an article on memory built-in self-repair (BISR). This article describes a cost and benefit model for evaluating the economic effectiveness of various memory BISR schemes and implementations.
This issue of D&T also features two interesting contributions to our Perspectives department. First, there is an extended summary of a report on system-in-package (SiP) technology written by FSA's SiP subcommittee. This report highlights SiP's unique value in bringing together several IC, package, assembly, and test technologies to create highly integrated products with optimized cost, size, and performance. FSA formed the SiP subcommittee in 2004 to investigate SiP technology issues and challenges and to study its main applications and business opportunities. The subcommittee recently conducted this SiP market and patent analysis study and released its findings to FSA member companies. We thank FSA for sharing this information with our readers.
Second, Intel's Priyadarsan Patra discusses some of the challenges and new requirements for effective validation of future system chips. Our industry is reaching the point at which a worst-case design approach is way too conservative, and a better-than-worst-case design is gradually becoming a necessity to further reduce the chip's power consumption and increase its clock rate. Such a shift in underlying design principles poses new validation and test challenges: A system could malfunction even in the absence of any bug or defect. Some sort of error resilience needs to be considered and designed into the system so that it can tolerate such failures, caused by corner conditions.
Finally, there is an interesting roundtable on multiprocessor SoC design. Organized by Bill Joyner (our roundtables editor) and moderated by Ahmed Jerraya at the 6th International Forum on Application-Specific Multi-Processor SoC (MPSoC 06), this roundtable summarizes seven panelists' views on the current state of multiprocessor SoC technology and new opportunities in this area.
I hope you enjoy this issue! If you have any feedback, please share it with us.
Editor in Chief
IEEE Design & Test