Issue No. 02 - March-April (2007 vol. 24)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.42
Functional verification remains a major bottleneck of the design process. One approach to combating this bottleneck is to combine multiple, complementary techniques. This issue examines recent progress in this direction. The issue also includes two Perspectives articles: an extended summary of a report on system-in-package technology by the FSA SiP subcommittee, and a discussion on challenges and new requirements for effective validation of future system chips. Finally, this issue includes an article on memory built-in self-repair (BISR) and a roundtable on the future of multiprocessor SoC.
functional verification, validation, SiP, multiprocessor SoC, BISR
T. Cheng, "Cocktail approach to functional verification," in IEEE Design & Test of Computers, vol. 24, no. , pp. 108, 2007.