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Design and test on chip for EMC

Fabian , PUCRS

Pages: pp. 502-503

The IEEE Computer Society's Test Technology Technical Council (TTTC) organized this panel as part of the 2006 EMC Europe International Symposium on Electro-mechanical Compatibility (, held in Barcelona, Spain, 4-8 September 2006. The panel addressed the recent explosion of the portable-electronics market and the increasingly hostile electro-magnetic (EM) environment in which these systems must operate. This scenario has intensified the need to include strict noise-immune parameters in design and test methods of SoCs. Focusing on the design of embedded systems for harsh environments, this panel tried to satisfy such a need. The panel addressed three challenging issues:

  • How do we design new reliable products with enhanced environmental awareness? In the field of test, design and subsequent test have given way to DFT techniques. Consequently, system dependability has driven the need for online testing for transient faults such as single-event upsets (SEU). It might be possible to reuse such on-chip resources for design for EMC (DF_EMC). The design, test, and EMC communities need to work together to minimize the cost of DF_EMC.
  • How can we predict system reliability in early design stages? IC designers should consider emission and susceptibility models for IP-core simulation and soft-error rate (SER) prediction when purchasing such products from core providers.
  • How effective are existing test procedures and standards at bringing such systems to the market? New standards and test procedures should scale down to 65-nm technology ICs running under clock rates far beyond 1 GHz. In this arena, IC designers should consider using EM direct coupling with ICs rather than conducted coupling at the board level toward the IC input pins.

Meanwhile, as semiconductor technologies move down the nanometer scale, SoC designers face increasing challenges: complexity, performance, and quality requirements continue growing while time to market and production cost are under great pressure to decrease. At the same time, system operation must cope with ever-decreasing power supply voltage levels. Hence, data storage must proceed with increasingly less electric charge, and data processing and communication must grow more quickly. This scenario significantly enhances the interaction of IP cores and SoCs with the environment, in both directions: EM emission and susceptibility. The final goal is to ensure SoC EMC.

New product developments must take into account the unwanted new roles that devices must assume: as an aggressor, and as a victim. Figure 1a summarizes the impact of technology trends on IC performance. Although supply voltage reduction raises the hope for less EM emission, this benefit is immediately neutralized by a drastically increased number of simultaneously switching transistors per die, combined with faster switching edges due to increasing clock rates. The final consequence is a net increase in the amount of total EM emissions. Additionally, core and peripheral power supply reduction increases EM susceptibility. At the same time, applications and customer satisfaction require ever-increasing system reliability and dependability—for safety or economic reasons, even in harsh environments, such as automotive, biomedical, and aerospace.


Figure 1   Technology progress over the years: impact of technology trends on ICs (a) and corresponding EMC model standards, research proposals, and I/O standards (b). (ICEM: IC emission modeling; LECCS: linear equivalent circuit and current source.)

Therefore, designers acting at different levels of system integration—IP core, SoC, system on a board, and system in a package—face a common challenge: developing new products with enhanced environmental awareness. This means system specifications must consider a new actor—the harsh environment in which the system must operate and meet customer expectations.

Studies show that one of the consequences of scaling down from 180-nm technology is that the SER induced by heavy-ion particles (transient radiation) on memory arrays remains roughly constant for memories fitting in the same silicon area. As technology scales down, the critical charge of memory cells decreases, thus increasing the probability of SEUs. The corresponding sensitive area of such cells also decreases in the same proportion, thus reducing the probability of SEUs. Ultimately, though, one effect offsets the other, and the final SER remains roughly constant. (For larger memory arrays, higher SERs are expected.)

The way EMI affects ICs is independent of the size of the memory cells' sensitive areas. Instead, IC susceptibility depends only on the memory cell's critical charge. In other words, the lower a memory cell's critical charge is, the lower the signal-to-noise ratio will be. As technology scales down, the EMI SER will increase even for memories with the same silicon area. Thus, the EM environment will compromise far more system reliability than transient radiation.

Additionally, designers must model IC behavior for emissions and immunity, and simulate such interactions as far as they can predict—devising tests that can uncover out-of-spec operations due to such interactions (see Figure 1b). IC emissions from EMC are far better understood and modeled than susceptibility. Hence, EMC standards for emissions of medium-complexity ICs are mature—for example, IC emission modeling (ICEM) and linear equivalent circuit and current source (LECCS) models, which thus far are limited to 1 GHz. However, EMC standards for susceptibility—such as the IC immunity model (ICIM) draft—are still under discussion by several committees composed of members from industry and academia. A strong demand for nanocircuits buildup from 65-nm technology running in excess of 1 GHz has motivated some research on more accurate models, such as x-ICEM.

The increasing complexity of ICs has led to a parallel increase in model complexity. SoCs are tightly bound to the use of IP-core-based design reuse methodologies. Extracting the emission and susceptibility models for a complete SoC would require several months, which is not compatible with an industrial design flow. Soon, it will be increasingly more important to associate design for EMC guidelines with current, standard IP-core design flows.


Clearly, there is a need to focus more on this problem along with other design constraints, and create avenues to roadmap successful solutions. Having understood the problem, the European Medea+EDA Roadmap ( web/communication/publ_ eda.php) has established a framework for handling EMC in SoC designs. But SoC researchers, engineers, and designers still have a lot of work to do to completely tackle this problem.

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