Issue No. 05 - September/October (2006 vol. 23)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.126
Sebasti? A. Bota , University of the Balearic Islands
Josep L. Rossell? , University of the Balearic Islands
Carol de Benito , University of the Balearic Islands
Ali Keshavarzi , Intel
Jaume Segura , University of the Balearic Islands
It is a well-known phenomenon that test-mode switching activity and power consumption can exceed that of mission mode. Thus, testing can induce localized heating and temperature gradients with deleterious results. The authors quantify this problem and propose a novel design scheme to circumvent it.
clock skew, clock distribution network, temperature, interconnect delay
C. d. Benito, S. A. Bota, J. L. Rossell?, A. Keshavarzi and J. Segura, "Impact of Thermal Gradients on Clock Skew and Testing," in IEEE Design & Test of Computers, vol. 23, no. , pp. 414-424, 2006.