Pages: p. 315
Organizer: A. Khoche, Agilent; moderator: P. Muhmenthaler, Infineon
Panelists: D. Apello, STMicroelectronics; I. Hartanto, Avago Technologies; T. Jackson, Cadence; W.T. Cheng, Mentor Graphics; and T. Williams, Synopsys
THE IEEE VLSI Test Symposium (VTS 06), which took place in Berkeley, California, 30 April–4 May, featured numerous special sessions, including panels, embedded tutorials, and hot topic presentations.
The panel on "Real-time volume diagnostics: requirements and challenges" discussed developing an environment to enable volume diagnostics. As we move along the technology nodes into the nanometer era, the initial and mature yield drop and the distribution of the yield detractor changes to include a large proportion of defects due to systematic design and process interactions. Simulating such a mechanism for prediction and avoidance is computationally very complex for any chips of a reasonable size. This forces us to identify such defects on the real silicon in production over a large volume using volume diagnostics. This panel confirmed the need for production-enabled diagnosis and identified the following as requirements and challenges:
The panel and audience also discussed the current state of the tools and agreed that the tools necessary to implement high-accuracy volume diagnostics might not be ready—for example, there is no diagnosis for failure due to signal integrity. Automatic test pattern generation tools still focus on screening, which needs to change. In addition, the panel also discussed the ownership of deploying such volume diagnostic systems and concluded that a multiparty partnership using standard data formats is the right way to implement such a system.