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Issue No. 02 - March/April (2006 vol. 23)
ISSN: 0740-7475
pp: 88-98
Mohd Fairuz Zakaria , Freescale Semiconductor, Malaysia
Melanie Po-Leen Ooi , Monash University Malaysia
Serge Demidenko , Monash University Malaysia
Zainal Abu Kassim , Freescale Semiconductor, Malaysia
Editor's note: High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in. --Phil Nigh, IBM Microelectronics
integral circuit testing, burn-in reduction, voltage stress, Weibull analysis
Mohd Fairuz Zakaria, Melanie Po-Leen Ooi, Serge Demidenko, Zainal Abu Kassim, "Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis", IEEE Design & Test of Computers, vol. 23, no. , pp. 88-98, March/April 2006, doi:10.1109/MDT.2006.50
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