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TABLE OF CONTENTS
Issue No. 06 - November/December (vol. 22)
ISSN: 0740-7475
From the EIC

Going 3D: Silicon and <em>D&T</em> (HTML)

Rajesh Gupta , Editor in Chief, IEEE Design & Test
pp. 493-494
Features

Demystifying 3D ICs: The Pros and Cons of Going Vertical (Abstract)

Christopher Mineo , North Carolina State University
W. Rhett Davis , North Carolina State University
Jian Xu , North Carolina State University
Stephen Mick , North Carolina State University
John Wilson , North Carolina State University
Michael Steer , North Carolina State University
Ambarish M. Sule , North Carolina State University
Hao Hua , North Carolina State University
Paul D. Franzon , North Carolina State University
pp. 498-510

3D Chip Stack Technology Using Through-Chip Interconnects (Abstract)

Peter Benkart , Infineon Technologies and University of Ulm
Alexander Kaiser , University of Ulm
Markus Bschorr , University of Ulm
Holger Huebner , Infineon Technologies
Arne Heittmann , Infineon Technologies
Andreas Munding , University of Ulm
Hans-Joerg Pfleiderer , University of Ulm
Erhard Kohn , University of Ulm
Ulrich Ramacher , Infineon Technologies
pp. 512-518

Placement and Routing in 3D Integrated Circuits (Abstract)

Tianpei Zhang , University of Minnesota
Brent Goplen , University of Minnesota
Yan Feng , University of Minnesota
Kia Bazargan , University of Minnesota
Sachin Sapatnekar , University of Minnesota
Hushrav Mogal , University of Minnesota
Cristinel Ababei , University of Minnesota
pp. 520-531

Physical Design for 3D System on Package (Abstract)

Sung Kyu Lim , Georgia Institute of Technology
pp. 532-539

Predicting the Performance of a 3D Processor-Memory Chip Stack (Abstract)

Aamir Zia , Rensselaer Polytechnic Institute
Okan Erdogan , Rensselaer Polytechnic Institute
Paul M. Belemjian , Rensselaer Polytechnic Institute
John F. McDonald , Rensselaer Polytechnic Institute
Philip Jacob , Rensselaer Polytechnic Institute
Russell P. Kraft , Rensselaer Polytechnic Institute
pp. 540-547

First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration (Abstract)

Kenneth Rose , Rensselaer Polytechnic Institute
Annie (Yujuan) Zeng , Rensselaer Polytechnic Institute
James (JianQiang) L? , Rensselaer Polytechnic Institute
Ronald J. Gutmann , Rensselaer Polytechnic Institute
pp. 548-555

Bridging the Processor-Memory Performance Gapwith 3D IC Technology (Abstract)

Ilya Ganusov , Cornell University
Martin Burtscher , Cornell University
Sandip Tiwari , Cornell University
Christianto C. Liu , Cornell University
pp. 556-564
Special ITC Section

X-Tolerant Test Response Compaction (Abstract)

Steven S. Lumetta , University of Illinois at Urbana-Champaign
Michael Mitzenmacher , Harvard University
pp. 566-574

A Novel Transition Fault ATPG That Reduces Yield Loss (Abstract)

Xiao Liu , Texas Instruments
Michael S. Hsiao , Virginia Polytechnic Institute and State University
pp. 576-584

IC Outlier Identification Using Multiple Test Metrics (Abstract)

Sagar S. Sabade , Texas Instruments
Duncan M. Walker , Texas A&M University
pp. 586-595
Book Reviews

Designing "Vary" Good Circuitry (HTML)

Sachin Sapatnekar , University of Minnesota
pp. 596-597
Panel Summaries

Panel Summaries (Abstract)

pp. 598-599
Conference Reports

2005 IEEE East-West Design and Test Workshop (Abstract)

Vladimir Hahanov , Kharkov National University of Radioelectronics
pp. 600
TTTC Newsletter

Test Technology TC Newsletter (Abstract)

pp. 602-603
Annual Index
The Last Byte

ITC is Cool (Abstract)

pp. 616
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