Issue No. 06 - November/December (2005 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.154
Subhasish Mitra , Intel
Steven S. Lumetta , University of Illinois at Urbana-Champaign
Michael Mitzenmacher , Harvard University
Nishant Patil , Intel
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression techniques attempt to do more testing with fewer bits. This article summarizes one such method, X-compact, which addresses how unknowns, the bane of compression and logic BIST techniques, are eliminated.
VLSI Test, Testability, Built-In Test
S. S. Lumetta, S. Mitra, M. Mitzenmacher and N. Patil, "X-Tolerant Test Response Compaction," in IEEE Design & Test of Computers, vol. 22, no. , pp. 566-574, 2005.