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Issue No. 06 - November/December (2005 vol. 22)
ISSN: 0740-7475
pp: 540-547
Aamir Zia , Rensselaer Polytechnic Institute
Okan Erdogan , Rensselaer Polytechnic Institute
Paul M. Belemjian , Rensselaer Polytechnic Institute
John F. McDonald , Rensselaer Polytechnic Institute
Philip Jacob , Rensselaer Polytechnic Institute
Russell P. Kraft , Rensselaer Polytechnic Institute
ABSTRACT
A primary bottleneck in the performance of a processor is in its communication with memory. By allowing the placement of processor and memory in adjacent layers, 3D design provides significant relief, reducing the communication latency. This article studies the impact of 3D design bycomparing the cycles per instruction of such a design with various alternatives.
INDEX TERMS
Cache memories, Simulation, Performance of Systems
CITATION
Aamir Zia, Okan Erdogan, Paul M. Belemjian, John F. McDonald, Philip Jacob, Russell P. Kraft, "Predicting the Performance of a 3D Processor-Memory Chip Stack", IEEE Design & Test of Computers, vol. 22, no. , pp. 540-547, November/December 2005, doi:10.1109/MDT.2005.151
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