Issue No. 05 - September/October (2005 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.104
Srinivasan Murali , Stanford University
Theocharis Theocharides , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
Luca Benini , University of Bologna
Giovanni De Micheli , Ecole Polytechnique Federale de Lausanne
Error resiliency is a must for NoCs, but it must not incur undue costs--particularly in terms of energy consumption. Here, the authors present anauthoritative discussion of the trade-offs involved in various error recoveryschemes, enabling designers to make optimal decisions.
Performance and Reliability, I/O and Data Communications
S. Murali, L. Benini, N. Vijaykrishnan, T. Theocharides, G. D. Micheli and M. J. Irwin, "Analysis of Error Recovery Schemes for Networks on Chips," in IEEE Design & Test of Computers, vol. 22, no. , pp. 434-442, 2005.