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Issue No. 05 - September/October (2005 vol. 22)
ISSN: 0740-7475
pp: 404-413
Andr? Ivanov , University of British Columbia
Cristian Grecu , University of British Columbia
Giovanni De Micheli , Ecole Polytechnique Federale de Lausanne
Resve Saleh , University of British Columbia
Partha Pratim Pande , Washington State University
For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.
VLSI, VLSI Systems, Automatic synthesis, Reliability, Testing, and Fault-Tolerance
Andr? Ivanov, Cristian Grecu, Giovanni De Micheli, Resve Saleh, Partha Pratim Pande, "Design, Synthesis, and Test of Networks on Chips", IEEE Design & Test of Computers, vol. 22, no. , pp. 404-413, September/October 2005, doi:10.1109/MDT.2005.108
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