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Issue No. 05 - September/October (2005 vol. 22)
ISSN: 0740-7475
pp: 393
Rajesh Gupta , Editor in Chief, <em>IEEE Design & Test</em>

A typical ASIC chip today is about 50 square millimeters of silicon containing about 50 million transistors on 130-nm process technology, operating at somewhere between 300 and 500 MHz. These parts come off, literally in the thousands, from 300-mm wafers—and in sufficient quantity cost around $5 each, no matter what you build with the digital CMOS circuits onboard. Thus, in addition to being the magical medium for enhanced integration, a chip is the enabler of many enhanced capabilities in electronics-based systems and user applications—from scientific computing and networking to mobile wireless and consumer multimedia.
Integration, of course, exists in all systems—not just microelectronics. Yet, the microelectronic chip package defines an interesting boundary and is an inflection point on the price-performance curves for most electronic systems. As components lift off the board and migrate inside a package, primarily onto a piece of silicon, they take with them a major fraction of the total system cost and enhance the system performance metrics at the same time. Once inside that package, however, the reality is very different from the board. At first, migration onto the same silicon led to multifunctional SoCs. Lately, cost-effective vertical stacking of multiple thinned-down dies in the same package has emerged with the integration of parts from multiple process nodes or device and circuit styles (flash, SRAM, pseudo SRAM, and so forth). An upcoming issue of D&T will cover vertical chip, or 3D, stacking; this issue explores on-silicon integration.
As SoCs continue down the path to smaller geometries and higher integration, their performance measures are changing dramatically. For instance, the increasing relative lengths of interconnects and their latencies naturally define local versus global regions within the chip. The larger the chip, the greater the disparity between local logic speeds and their interconnect latencies: Round-trip delay, even in a typical chip today, easily exceeds the clock cycle time. So before long, researchers started looking into architecting on-chip component interconnects. For the most part, interconnect solutions (such as hierarchical interconnect and connection topologies) from board-level designs ported over—with little modification—to on-chip interconnect structures as well. However, as the community looked deeper, important differences emerged, such as trade-offs among latency and bandwidth considerations, silicon area, power consumption, defect tolerance, and verification and CAD methodology issues.
Our guest editors, Giovanni De Micheli and André Ivanov, have pulled together an excellent set of five articles along with their introductory piece on challenges in networks on chips. These articles analyze various NoC architectures (such as star and mesh networks) in terms of efficient communication mechanisms, describe the Æthereal NoC, explore error recovery schemes for NoCs based on packet-switched communication fabrics, and discuss interconnect structures for reconfigurable circuit blocks.
Our general-interest articles discuss the modeling and cosimulation of virtual IP blocks for SoCs and the use of dynamically reconfigurable hardware for enhanced media processing. Continuing our coverage of the Design Automation Conference, D&T's Yervant Zorian interviews Bernard Meyerson, a keynote speaker at this year's DAC.
Finally, it is my pleasure to welcome Sachin Sapatnekar to the D&T editorial board. He will be area editor for performance issues in IC design, an area of growing importance. As D&T expands, it continues to seek new talent and volunteers to help with the magazine's content and organization. If you are interested, please do drop us a line. In the meantime, I hope you enjoy this issue!

Rajesh Gupta, Editor in Chief
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