Issue No. 04 - July/August (2005 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.89
Rajeev R. Rao , University of Michigan, Ann Arbor
David Blaauw , University of Michigan, Ann Arbor
Dennis Sylvester , University of Michigan, Ann Arbor
Anirudh Devgan , Magma Design Automation
Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.
Fault-Tolerance, G.4.g Reliability and robustness, B.7 Integrated Circuits
R. R. Rao, A. Devgan, D. Blaauw and D. Sylvester, "Modeling and Analysis of Parametric Yield under Power and Performance Constraints," in IEEE Design & Test of Computers, vol. 22, no. , pp. 376-385, 2005.