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Issue No. 04 - July/August (2005 vol. 22)
ISSN: 0740-7475
pp: 306-315
Andr? DeHon , California Institute of Technology
Helia Naeimi , California Institute of Technology
ABSTRACT
To tolerate defects in molecular electronics, the authors propose techniques to bypass defective resources during the logic mapping phase. These techniques take advantage of intrinsic redundancy in molecular crossbars to tolerate defective nanowires and nanocrossbars. The proposed greedy mapping algorithm can tolerate a defect density of 10% with very low area overheads.
INDEX TERMS
Redundant design, Reconfigurable hardware, Built-in tests, Reliability, Testing, and Fault-Tolerance, Testing strategies, integrated circuits, Logic Arrays, Advanced Technologies
CITATION
Andr? DeHon, Helia Naeimi, "Seven Strategies for Tolerating Highly Defective Fabrication", IEEE Design & Test of Computers, vol. 22, no. , pp. 306-315, July/August 2005, doi:10.1109/MDT.2005.94
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