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Issue No. 03 - May/June (2005 vol. 22)
ISSN: 0740-7475
pp: 232-239
Greg Yeric , HPL Technologies
Ethan Cohen , HPL Technologies
John Garcia , HPL Technologies
Kurt Davis , HPL Technologies
Esam Salem , HPL Technologies
Gary Green , HPL Technologies
Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL—an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM.
systematic yield loss, test structure, BEOL, infrastructure IP, process monitoring, silicon debug, DFM

E. Cohen, E. Salem, G. Yeric, G. Green, K. Davis and J. Garcia, "Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below," in IEEE Design & Test of Computers, vol. 22, no. , pp. 232-239, 2005.
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