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Issue No. 03 - May/June (2005 vol. 22)
ISSN: 0740-7475
pp: 214-222
Dong Hyun Baik , University of Wisconsin-Madison
Kewal K. Saluja , University of Wisconsin-Madison
Charlie Chung-Ping Chen , University of Wisconsin-Madison
Jeng-Liang Tsai , University of Wisconsin-Madison
This article proposes clock skew scheduling as a tool to address causes of performance-related circuit yield loss. It is an interesting example of how managing circuit-level parameters can have a direct impact on yield metrics and, therefore, a clear example of the direction of DFM research.
clock skew scheduling, performance-related circuit yield loss, circuit-level parameters, DFM
Dong Hyun Baik, Kewal K. Saluja, Charlie Chung-Ping Chen, Jeng-Liang Tsai, "Yield-Driven, False-Path-Aware Clock Skew Scheduling", IEEE Design & Test of Computers, vol. 22, no. , pp. 214-222, May/June 2005, doi:10.1109/MDT.2005.75
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