• Design for manufacturable patterns. These techniques include novel design flows based on advanced resolution enhancement techniques (RETs); architecture, logic, circuit, and layout optimization for future lithography nodes; and comparisons between design-rule- versus tool-based DFM methodologies.
• New manufacturability-oriented design blocks. These advanced forms of infrastructure IP are for manufacturability issue detection, analysis, and correction; DFM via adaptive circuits, logic, and architectures; and defect-tolerant designs.
• Improved interaction at the design-manufacturing interface. At the interface between the two, new data preparation flows address the data size explosion problem. Design techniques for reducing mask-related costs are also important.
• Design for yield enhancement. Chips now incorporate embedded diagnosis and debug functions, and built-in process monitors and other features to perform embedded measurement. They are capable of repair analysis and self-reconfiguration, and can supply data to support statistical design, power and performance analysis, and optimization. Other techniques include variability-aware design and behavioral or logic synthesis for manufacturability.
• Domain-specific DFM. Specialized DFM covers analog and mixed-signal circuits, and 3D designs. One particular technique, manufacturable power grids, is useful for adapting the power delivery system to manufacturing-related performance unpredictability.
• Test-oriented DFM. This class of DFM includes techniques for manufacturability improvement via test and DFT, including test-based diagnosis, defect-based testing, failure analysis, and test-based yield learning.
Juan-Antonio Carballo is currently a partner in IBM's Venture Capital Group, responsible for semiconductors, EDA, and open systems. He previously led research in the design and manufacture of adaptive communications chips at IBM Research, where he filed more than 20 patents in systems and circuit design, design economics, and design management. Carballo has a BS and an MS in telecommunications engineering from the Universidad Politecnica de Madrid, an MBA from College des Ingenieurs in Paris, and a PhD in electrical engineering from the University of Michigan. He chairs the International Technology Roadmap for Semiconductors design and system drivers chapters, and is the chair elect of the IEEE Committee on Design Automation.
Yervant Zorian is vice president and chief scientist of Virage Logic. He previously was the chief technology advisor of LogicVision and a Distinguished Member of Technical Staff at Bell Labs. Zorian has an MSc in computer engineering from the University of Southern California, a PhD in electrical engineering from McGill University, and an executive MBA from the Wharton School of Business, University of Pennsylvania. He is the IEEE Computer Society vice president for conferences and tutorials, founder and chair of IEEE 1500 Working Group, and a Fellow of the IEEE.