Issue No. 03 - May/June (2005 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.59
Rajesh Gupta , Editor in Chief, <em>IEEE Design & Test</em>
The design-manufacturing interface (DMI) is one of the most critical junctions in the chip industry. For years, designers have debated the interplay of technologies on both sides of this interface. In this issue, D&T examines another current topic that deeply touches this interface: design for manufacturability (DFM). Manufacturability today goes beyond the traditional focus on yield and reliability, from achieving manufacturing-cost advantages to overcoming the enormous physics challenges faced by device and process engineers at the 65- and 45-nm nodes. Accordingly, DFM seeks to expand chip design considerations, exploiting optimizations beyond product engineering all the way to issues in semiconductor process engineering. Although DFM alone cannot surmount the tremendous device engineering challenges posed by future processes, there is no question that it can make manufacturability easier. For example, designs for manufacturable patterns can incorporate advanced resolution enhancement technologies, and infrastructure IP can help in the detection and analysis of manufacturing defects. Other DFM strategies include adaptive circuits, logic, and architecture; reducing data explosion across the DMI; embedded diagnosis and debug functions; built-in process monitors and embedded measurements that go beyond in-situ process monitoring to the failure analysis of manufactured parts; DFM for mixed-signal circuits; and so on.
Last year at this time, D&T examined several strategies that designers are beginning to explore to improve yield and reliability. This issue examines DFM techniques that fundamentally alter the design flow. One way to accomplish this is to use manufacturability as a criterion for design optimization at various stages of the design process, thus fixing the design or the design flow, as opposed to the traditional focus on improving reliability. Guest editors Juan-Antonio Carballo and Yervant Zorian have put together this special issue with four articles that examine fundamental changes to the DMI; the use of model-driven as opposed to rule-driven design and design verification; advances in DFT that increase yield learning and clock-skewing in designs for improved manufacturing yield; and an infrastructure for improved silicon debug, yield characterization, and yield ramp.
The general interest articles include a review of sequential equivalence verification and an article on soft errors in computing systems.
Our departments include a D&T Perspectives on deep-submicron technologies by Bob Madge and an interview with Irwin Jacobs, cofounder, chairman, and CEO of Qualcomm. In this interview, Irwin relates his experiences as a technologist and the genesis of arguably the most successful company in wireless communications, which is also the largest and leading fabless semiconductor design company.
Once again, it is time for the Design Automation Conference! This issue previews important DAC items. The July-August issue will cover the highlights of the DAC program and its buzz. With over 10,000 attendees, DAC is the hub of activity for the electronic design and design automation community. This year, DAC is also very special for the EDA community because of the recent announcement of the emerging IEEE Council on Electronic Design Automation (C-EDA). The emerging council reflects the EDA community's desire to organize its various technical activities and volunteer resources to advance the field, its profession, and the industry. Certainly, this is a time of exciting developments in EDA, and D&T looks forward to covering them in upcoming issues.
Editor in Chief, IEEE Design & Test