Issue No. 02 - March/April (2005 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.48
Grant Martin , Tensilica
A few years ago, Sun Microsystems used the slogan, "the network is the computer," to promote its products and to alert people to a profound change in computing-use models. With the growth in cell phones, digital cameras, portable music players, wireless e-mail, GPS sensors, and automotive map displays that rely on wired and wireless networks, you might be tempted to say "the network is my post office, my map, my stereo system, my photo album …" and so on.
If the network is a vital part of our electronics macrocosm, what of the microcosm that is so fundamental in all these products—the complex ICs and SoC devices on which they are built? It is now evident that SoC design is evolving toward a foundation based on chip-level networks. Indeed, the network is becoming the chip.
A shift to network-on-chip (NoC) design is not easy for design teams unless they possess the correct knowledge and tools. Moving from function-centric to NoC design requires an orthogonal change in design approach: the starting point is a network of collaborating functional blocks; interconnect is no longer just an afterthought. Designers must work at several levels of design abstraction: circuit, block, and system; detailed analysis of transistor and wiring-based effects; scheduling and routing algorithms; and advanced architectural modeling.
Interconnect-Centric Design for Advanced SoC and NoC, by editors Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch (Springer, 2004, ISBN 1-4020-7835-8, 453 pp., $135), is a useful tool to help a design team gain the cross-disciplinary knowledge required to more effectively design complex SoCs. The book is a collection of edited chapters written by various experts on NoC and on-chip communications design; the editors contributed to several of the chapters and, for the others, drew on several colleagues—including those participating in Complain, the Finnish-Swedish Excite research project. The editors have carefully chosen the topics in this volume to reflect the multiple levels and types of design knowledge required to gain an appreciation of the field.
The book starts at the fundamental physical and electrical level with an introductory chapter by Jan Rabaey of the University of California, Berkeley; he makes the case for an evolution to NoC. The four following chapters deal with circuit and wire-centric design and analysis: Chapter 2 discusses wires as fundamental interconnect structures and outlines their delay, noise, crosstalk, interference, and other physical and electrical effects. Chapter 3 dives into details of global interconnect analysis, focusing on analytical methods to support design decisions in such areas as buffer and repeater insertion, and power supply noise analysis. Chapter 4 extends this analysis to detailed physical design of repeaters and wire sizing, shaping, and tapering. Chapter 5, the final chapter in this section, deals with designing distributed clocking networks for high-performance SoCs.
Part 2 of the book deals with logical and architectural issues; it contains five chapters on error-tolerant interconnect design, power reduction coding for buses, bus structures in NoC, transitioning from on-chip buses to on-chip networks, and arbitration and routing schemes for on-chip packet networks. Of special interest is chapter 7 (on power reduction coding) by Paul Sotiriadis of Johns Hopkins University. This chapter provides a detailed mathematical analysis and explication of fundamental theorems in information theory, and it offers analysis techniques for determining the maximum possible power reduction for bus-based designs with given numbers of interconnect lines. Chapter 9 is also fundamental—it details the rationale for moving from bus-based, on-chip interconnect to circuit- and packet-switched NoC approaches. The bus-based approach imposes limits on scalability, testability, latency, and modularity. Today's increasingly complex IP-based SoCs demand removing those limits through a switched-network approach.
Part 3 moves the discussion to design methodology and tools. Chapter 11 (on self-timed design for reducing noise and peak current) introduces the topic of asynchronous on-chip circuit design, with detailed analysis of area and power trade-offs on example circuits. The three following chapters deal with system-level analyses and tools—one on formal communications modeling, one on NoC system-level modeling and simulation (by Jan Madsen and colleagues from the Technical University of Denmark), and one on the Sonics socket-based design approach and associated tools.
Finally, Part 4 concludes with two chapters about applications. The first (by Kees Goossens and colleagues from Philips) gives a good description of some complex, real-life SoCs that use advanced on-chip communications and interconnect design. The chapter focuses on the Philips Viper and Viper2 chips used in digital multimedia devices; the discussion extends to future SoCs evolving from traditional bus-based design toward real NoC, as do Viper and Viper2. The book's final chapter (by researchers from several Finnish universities, including two of the book's editors) discusses a research multimedia-processing platform using the Proteo packet-switching network communication backplane, thus pushing real use of on-chip networks closer.
Clearly, the book covers an impressive breadth of topics, and several of the discussions have sufficient depth to provide real insight on their topics. Bringing in industrial authors (such as Drew Wingard of Sonics and authors from Philips) grounds parts of the book with the current state of the art in industrial practice; and presenting leading research results provides good pointers to future development. Each chapter surveys the relevant literature in its particular topic area and provides an extensive reference list for further reading.
In fact, the book would have been stronger if it had included a little more from the industrial community and more leading semiconductor companies pursuing advances in on-chip interconnect—for example, Intel, IBM, and STMicroelectronics all come to mind as industrial companies pursuing advanced interconnect and on-chip approaches. In addition, some of the topics—such as formal communications modeling (Chapter 12)—lack sufficient elaboration and application to real design problems to justify their inclusion in the book; this approach might have benefits in the future, but it needs to be applied outside the research setting.
But, all in all, this book is quite useful for educating any SoC design team in many of the areas critical to adapting their designs to future generations of interconnect. It can also be a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Designers and design educators should take a close look at this book.