Issue No. 01 - January/February (2005 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.2
Gustavo Neuberger , Federal University of Rio Grande do Sul
Fernanda Gusmao de Lima Kastensmidt , Federal University of Rio Grande do Sul
Ricardo Reis , Federal University of Rio Grande do Sul
Editors' note: Modern SoC architectures manufactured at ever-decreasing geometries use multiple embedded memories. Error detection and correction codes are becoming increasingly important to improve the fault tolerance of embedded memories. This article focuses on automatically optimizing classical Reed-Solomon codes by selecting the appropriate code polynomial and set of used symbols.<div>—Dimitris Gizopoulos, University of Piraeus; and Yervant Zorian, Virage Logic</div>
G. Neuberger, F. G. de Lima Kastensmidt and R. Reis, "An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories," in IEEE Design & Test of Computers, vol. 22, no. , pp. 50-58, 2005.