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TABLE OF CONTENTS
Issue No. 06 - November/December (vol. 21)
ISSN: 0740-7475
Special Features
EIC Message

Verification synergies (HTML)

Rajesh Gupta , Editor in Chief, <em>IEEE Design & Test</em>
pp. 457
Features

A Layered Adaptive Verification Platform for Simulation, Test, and Emulation (Abstract)

Wolfgang Ecker , Infineon Technologies
Martin Zambaldi , Infineon Technologies
Renate Henftling , Infineon Technologies
Matthias Bauer , Infineon Technologies
pp. 464-471

Linking Simulation with Formal Verification at a Higher Level (Abstract)

Serdar Tasiran , Ko? University
Yuan Yu , Microsoft Research
pp. 472-482

TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification (Abstract)

Young-Il Kim , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology Integrated Circuit Design Education Center
pp. 484-493
Special Features

Success-Driven Learning in ATPG for Preimage Computation (HTML)

Shuo Sheng , Mentor Graphics
Michael S. Hsiao , Virginia Tech
pp. 504-512

On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations (Abstract)

Giovanni De Micheli , Stanford University
Paolo Ienne , Swiss Federal Institute of Technology Lausanne
Fr?d?ric Worm , Swiss Federal Institute of Technology Lausanne
Patrick Thiran , Swiss Federal Institute of Technology Lausanne
pp. 524-535

Jitter Measurements of High-Speed Serial Links (Abstract)

Martin L. Schmatz , IBM Zurich Research Laboratory
Marcel A. Kossel , IBM Zurich Research Laboratory
pp. 536-543

A Self-Correcting Active Pixel Sensor Using Hardware and Software Correction (Abstract)

Israel Koren , University of Massachusetts, Amherst
Zahava Koren , University of Massachusetts, Amherst
Sunjaya Djaja , Simon Fraser University
Glenn H. Chapman , Simon Fraser University
Desmond Y.H. Cheung , Simon Fraser University
Yves Audet , Ecole Polytechnique, Montreal
pp. 544-551

Designing Fault-Tolerant Techniques for SRAM-Based FPGAs (Abstract)

Renato Fernandes Hentschke , Federal University of Rio Grande do Sul
Gustavo Neuberger , Federal University of Rio Grande do Sul
Fernanda Gusmao de Lima Kastensmidt , State University of Rio Grande do Sul
Luigi Carro , Federal University of Rio Grande do Sul
Ricardo Reis , Federal University of Rio Grande do Sul
pp. 552-562

Enhancing Yield at the End of the Technology Roadmap (Abstract)

Bipul C. Paul , Purdue University
Kaushik Roy , Purdue University
pp. 563-571

Web-Based Energy Exploration Tool for Embedded Systems (Abstract)

Yongsoo Joo , Seoul National University
Hyeonmin Lim , Seoul National University
Youngjin Cho , Seoul National University
Ikhwan Lee , Samsung Electronics
Hyung Gyu Lee , Seoul National University
Naehyuck Chang , Seoul National University
Hojun Shim , Seoul National University
Yongseok Choi , Seoul National University
pp. 572-586
Departments

Book Reviews (HTML)

pp. 590-591

System-level design language standard needed (Abstract)

Victor Berman , Cadence Design Systems
pp. 592-593

Conference Reports (Abstract)

Raimund Ubar , Tallinn University of Technology
Vladimir Hahanov , Kharkov National University of Radio Electronics
pp. 594-595

DATC Newsletter (Abstract)

pp. 596
The Last Byte

Design illiteracy (Abstract)

Scott Davidson , Sun Microsystems
pp. 608
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