Issue No. 06 - November/December (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.86
Naran Sirisantana , Intel
Bipul C. Paul , Purdue University
Kaushik Roy , Purdue University
<it>Editors' note: </it>Scaled manufacturing technologies require advanced techniques for improving device reliability and production yield. This article presents a transistor-level redundancy technique for manufacturing devices with low vulnerability and improving yield in future circuits. The technique relies on appropriate design style selection and controlled redundancy to achieve area and power trade-offs. <it>—Dimitris Gizopoulos, University of Piraeus</it>
B. C. Paul, K. Roy and N. Sirisantana, "Enhancing Yield at the End of the Technology Roadmap," in IEEE Design & Test of Computers, vol. 21, no. , pp. 563-571, 2004.