Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation
Issue No. 06 - November/December (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.87
Jayanta Bhadra , Freescale Semiconductor
Narayanan Krishnamurthy , Freescale Semiconductor
Magdy S. Abadir , Freescale Semiconductor
<it>Editor's note:</it> This article, from the Motorola (now Freescale) PowerPC design group, presents an interesting synergy among test, equivalence verification, and constraints. The authors use RTL, gate, and switch models of a design in two different flows—one for test and one for functional verification—to show that rectifying constraints and merging tests between the two flows saves significant presilicon debug effort.
Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir, "Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation", IEEE Design & Test of Computers, vol. 21, no. , pp. 494-502, November/December 2004, doi:10.1109/MDT.2004.87