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Issue No. 06 - November/December (2004 vol. 21)
ISSN: 0740-7475
pp: 484-493
Young-Il Kim , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology Integrated Circuit Design Education Center
<it>Editor's note:</it> This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral testbenches enables better partitions, resulting in lower communication costs between the two components. <it>—Sharad Malik, Princeton University</it>

Y. Kim and C. Kyung, "TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification," in IEEE Design & Test of Computers, vol. 21, no. , pp. 484-493, 2004.
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