Issue No. 06 - November/December (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.94
Serdar Tasiran , Ko? University
Yuan Yu , Microsoft Research
Brannon Batson , Intel
<it>Editor's note: </it>This article uses simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. —<it>Carl Pixley, Synopsys</it>
B. Batson, S. Tasiran and Y. Yu, "Linking Simulation with Formal Verification at a Higher Level," in IEEE Design & Test of Computers, vol. 21, no. , pp. 472-482, 2004.