Issue No. 05 - September/October (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.54
Highlights of the 10th IEEE International On-line Testing Symposium
Attendees actively participated in the 10th edition of the online-testing series of events, which started as a workshop in Nice, France, in 1995. The IEEE International On-Line Testing Workshop (IOLTW) was the creation of two cofounders: Michael Nicolaidis and Yervant Zorian. It began as an idea that was timely—the application domain of electronic systems was growing, as were system complexity and requirements, in terms of performance, quality, dependability, safety, and security. Today, the demand for cost-effective online testing techniques has increased dramatically with the introduction of deep-submicron and nanotechnologies. The growing interest justified the transformation of the workshop into a symposium—now called the IEEE International On-Line Testing Symposium (IOLTS)—in 2003.
At this year's event, held 12-14 July 2004 in Madeira, Portugal, keynote speaker Vinod Agrawal (founder and chairman of the board of LogicVision) talked about "A Pragmatic Approach to Online Testing" and set an underlying theme that remained pervasive throughout the symposium. What was the concept put forward to IOLTS attendees? "Pragmatic means widely used." The advice was clear: For online testing techniques to take center stage, they must have a set of features to make them widely accepted as part of the design flow for new products. For instance, scan design can boast a 0% overhead, because it is part of the design process! Agrawal urged researchers to deliver solutions that might, as much as possible, be implemented by existing design tools and, thus, show mainstream potential. He also encouraged researchers to listen to mainstream customers: They usually come up with very interesting ideas.
There was lively presentation and discussion of research results covering timing and transient faults (for test, diagnosis, or fault tolerance), and of core topics of online testing such as self-testing and self-checking circuits, concurrent error detection (CED), fault tolerance based on error correction code (ECC), and microprocessor online testing. There was also focus on dependability, safety, and security—emerging themes that are becoming more relevant for a wider range of applications, and for which cost-effective (thus, pragmatic) solutions are crucial.
Two panels drew much attention and participation from the audience. The first, "On the Emerging Field of Reliability and Dependability Challenges," was organized and moderated by Yervant Zorian (Virage Logic). Michael Nicolaidis (iRoC Technologies) stressed the growing concern about the sensitivity of electronic systems to environmental disturbances, such as single-event upsets (SEUs), even at ground level. Hans-Joachim Wunderlich (University of Stuttgart) focused on the automotive sector, reminding participants that there are no chips in the field—there are systems. People buy cars, and in such products, consumers expect that the electronics systems—now 20% of a car's production cost, as Eberhard Boehl of Robert Bosch GmbH pointed out—are dependable. Thus, dependability is now a key marketing request.
The second panel, organized by Rob Aitken (Artisan Components), focused on "Reliability Implications of Statistical Design." In this panel, André Nieuwland (Philips Research Laboratories) stated, "We should start designing reliable systems with unreliable components." Abhijit Chatterjee (Georgia Institute of Technology) stressed the importance of looking closely at yield versus performance trade-offs. Kaushik Roy (Purdue University) discussed the eventual need to use leakage sensors and adaptive techniques to deal with nanotechnology systems. John Hayes (University of Michigan) mentioned that designers should not push technology too far: Experience shows that it is better to replace a problem technology with a better technology.
If dependability and availability are important for you, please plan to participate in the next IEEE International On-Line Testing Symposium to be held 11-13 July 2005. For more details, go to http://tima.imag.fr/conferences/iolts.
First IEEE Silicon Debug and Diagnosis Workshop
Debug examines what to do when a circuit does not behave as intended; it is a requirement in the modern product creation flow. Unfortunately, processes related to debug and diagnosis can become unpredictably expensive time sinks. As a result, the IEEE International Workshop on Silicon Debug and Diagnosis (SDD) formed to find solutions and promote the exchange of practical ideas in this area.
The first SDD workshop took place in conjunction with the European Test Symposium at the Ajaccio Convention Center in Corsica, France, 26-27 May 2004. The workshop was well attended, with 36 participants from semiconductor and electronic system manufacturers; intellectual-property providers; test and measurement and EDA companies; and advanced research labs. The audience possessed broad practical interests in areas such as prototype turn-on, diagnostic flows, silicon editing, on-chip design for debug, and test quality improvement.
The workshop's format was a one-and-a-half-day discussion forum focused on papers, panels, and audience comments. After opening with a tutorial on debug and diagnosis fundamentals, the workshop quickly centered on defining the SDD problem space and reconciling the terminology used among the diverse participants.
Papers and discussions probed for a wish list of items that a debug and diagnosis portfolio should contain. Fundamentally, it was agreed that the acceptability afforded to design for testability should extend to debug and diagnosis. That is, the test community must move beyond the pass/fail manufacturing test philosophy toward providing control and observing ICs for purposes of debug. For instance, this might include the ability to "poke around" the chip during turn-on, similar to the way you manipulate a simulation. The ability to logically control clocking, change selected state variables, perform experiments based on user-defined triggers or internal flags, perform timing-oriented measurements, and quickly extract/capture circuit states while preserving the functional sequence would all aid in achieving this objective.
Debug and diagnosis provide information necessary to fix the circuit, the test environment, test program quality, the fabrication process—fix something. To gather such information, the workshop presented examples of on-chip and in-system monitoring. Attendees also discussed the use of ATE (both conventional and DFT testers) for data gathering and scan-based debug.
Of course, these are just the tip of the iceberg—many shortcomings exist in technology. SDD is not yet as formalized and commercialized as well-known structural testing. Tools, techniques, usable equipment, and data are all open issues. Because many of the structures and approaches require functional circuit information, the appropriate communication model, documentation, and problem ownership must exist between the people designing the circuit and those performing the debug/diagnosis tasks. It is well-known that in a contemporary environment, these parties might be globally distributed and/or outsourced. Even when debug is successful, the error must be reproducible on a manufacturing platform (the platform itself must be set up so that it does not introduce false failures). Further, as discussed in presentations on new silicon editing techniques (for example, there was a focus on ion beam and laser stimulation), a logical root cause is typically confirmed via expensive physical techniques. The business model for this in a disaggregated supply chain could be an opportunity.
Planning for the next SDD workshop is currently under way. The workshop will likely emphasize examples and case studies. The working group of participants will continue to explore the SDD issue and select topics for greater focus. There will also be evaluation of potential areas for standardization.
Southwest Test Workshop 04
The Southwest Test Workshop returned to the Paradise Point Resort in San Diego, California, 6-9 June 2004, for its 14th annual meeting. It is the only IEEE-sponsored conference specializing in wafer- and die-level test technology, and 406 wafer test professionals attended this year, up 75% from 2003. It was acknowledged the decision to return to the San Diego resort hotel was motivated by popular demand, but the dramatic attendance growth was probably the result of a much better semiconductor economy as well as the great locale.
Jerry Broz, the program chair from International Test Solutions, and the rest of the Steering Committee did an excellent job providing 30 technical presentations. The conference is a probe technology forum with a balanced mixture of semiconductor manufacturers and members of the technical staff from probe product and service suppliers (a few salesmen also sneak in). The program reflected that mix with 40% of the presentations from manufacturers, 43% from the suppliers, and 17% joint presentation. The hot topics this year were memory and high-power probing, probe process characterization and troubleshooting, and reduced-force probing for low-k dielectrics.
There were also some interesting new products introduced in carefully disguised sales pitches, but that's what the attendees expect.
The conference had tabletop exhibits for the first time; 28 product and service suppliers participated: 16 probe card manufacturers, four probe suppliers, two probe card analyzer companies, two probe needle suppliers, and a few other related equipment and service providers. The exhibit area opened only after the general session ended. There were three 2-hour viewing periods, and cocktails and hors d'oeuvres encouraged the attendees to visit the exhibits. However, the Steering Committee made it clear the exhibits were to complement the technical program, and the conference would not become a sales show. The exhibitors and the attendees seemed to enjoy the addition to the conference, and one attendee said it was the only place he has ever seen all the key probe suppliers in one spot at one time. It might be a little premature to announce the death of the Semicon trade show, but small exhibits at focused workshops certainly seem to be successful.
As usual, there were plenty of social activities to give the attendees time for informal discussions and networking. After an intense day of probe test technology, there was a Team Techno trivia contest at the hotel's Barefoot Bar, and everyone enjoyed a sunset dinner cruise around Mission Bay. On Tuesday afternoon, the workshop organized bus transportation and tickets to SeaWorld, and some attendees played miniature golf on the hotel's course. After the trivia and golf awards banquet on Tuesday evening, Kevin Grazier of Jet Propulsion Laboratory presented "The Search for Water in the Universe," complete with some great slides from two Mars Rover landings in January. All the presentations, and the answers to the techno trivia contest, will soon be available on the Southwest Test Workshop's Web site at http://www.swtest.org.
7TH IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Elena Gramatová Program vice chair, DDECS 2004
The 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004) took place in the High Tatra Mountains of North Slovakia, 18-21 April 2004. DDECS 2004 is a continuation of the workshop series, organized annually in Central Europe, that offers a forum for research and practical applications in the design, test, and diagnosis of microelectronic circuits and systems. Over the years, DDECS has undergone healthy growth in terms of both submissions and attendees, and has now become one of the major scientific events organized in Central Europe in the target research areas. This year, the workshop received 86 submissions (75 regular and 11 student papers) from 30 countries in Europe, Asia, and North America—26 of which (23 regular and 3 student papers) the program committee selected for oral presentation.
The technical program consisted of three-day single-track sessions with the support of three excellent keynote speeches. In the first speech, Hans-Joachim Wunderlich of the University of Stuttgart (Germany) addressed the test field. His speech "From BIST to BISD" dealt with the state of the art and current trends in BIST techniques, as well as their reuse for diagnosis and defect-tolerance requirements. Manfred Glesner of Darmstadt University of Technology (Germany) presented the second talk, "System Design Challenges in Ubiquitous Computing Environments." This talk gave insight into the challenges imposed in SoC design of ubiquitous systems with a special focus on reconfigurable architectures and embedded systems. The third keynote speaker, Dominique Borrione of TIMA (France's laboratory of Techniques of Informatics and Microelectronics for Computer Architecture) highlighted techniques targeted to verification and validation in her talk "Multi Paradigm Formal Models for Circuit Validation and Verification."
The program also included a panel session entitled "Design and Test Education and Training in Europe—What are the Main Challenges?" Zebo Peng of Linköping University chaired the session, which included six excellent panelists: Christian Landrault of LIRMM (Laboratory of Data Processing, Robotics, and Microelectronics in Montpellier, France), Paulo Teixeira of IST/INESC-ID (Instituto Superior Técnico and Institute of Engineering of Systems and Computers, Inquiry and Development; in Lisbon, Portugal), Sybille Hellebrand of the University of Innsbruck, András Pataricza of the Budapest University of Technology and Economics, Raimund Ubar of the Tallinn University of Technology, and Norbert Fristacky of the Slovak University of Technology, Bratislava. One day before the workshop, two tutorials were organized under the 5FP Project, IST 2000-30193 Reason: "Defect-oriented Testing" and "Additional Hardware for IC Testability Improvement." Lecturers from the Reason project countries gave the tutorials; Michel Renovell of LIRMM presented one invited lecture, "Realistic Fault Models for SPOT Defects." Additionally, the DDECS workshop series featured for the first time a student presentation session, which included three regular presentations and five posters from five European countries.
The participants found DDECS 2004 to be fruitful and interesting with many informal discussions during presentations, before the poster session, and during the well-organized social event and banquet.