Issue No. 04 - July/August (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.22
Ming-Jun Hsiao , National Tsing Hua University
Tsin-Yuan Chang , National Tsing Hua University
Jing-Reng Huang , National Tsing Hua University
On-chip timing-measurement units are needed because accessibility to internal nodes in SoCs is very limited, and performing time interval measurements using automatic test equipment is very difficult and expensive. This article presents a parametric timing measurement solution, which uses self-timed techniques and delivers high linearity and improved accuracy, at low risk of measurement error.
Ming-Jun Hsiao, Tsin-Yuan Chang, Jing-Reng Huang, "A Built-In Parametric Timing Measurement Unit", IEEE Design & Test of Computers, vol. 21, no. , pp. 322-330, July/August 2004, doi:10.1109/MDT.2004.22