, University of British Columbia
, Northeastern University
, University of Bologna
Pages: pp. 274-276
It is with great pleasure that we introduce the special issue on Testing at MultiGbps Rates to the IEEE Design & Test readership. Manufacturing today's high-performance digital systems requires VLSI testing at speeds of multigigabits per second (multiGbps). For this special issue, we've selected four articles to cover a wide spectrum of techniques and applications critical to testing at multiGbps rates. In these articles, outstanding researchers cover experimental and speculative topics. As with all special issues, these topics represent only the publicly available literature currently provided by the technical community.
Recent years have seen the rapidly growing prominence of new techniques for testing ICs and systems with innovative features to allow high quality and fast test time. High-density, core-based ICs have recently gained popularity, yet the complexity of these chips can slow down product development and increase cost rather than provide high performance and profit margins in manufacturing. The new economy, the rising role of new technologies (such as SoC), and escalating costs for developing new products are forcing the electronic industry to reexamine existing approaches to design and test. For innovative products, the development of new technological environments promises to provide the greatest productivity increases—and therefore, the fastest time-to-market—while keeping costs under control. However, testing and debugging these devices are very difficult problems. Moreover, the industry recognizes that testing costs are escalating faster than other costs related to the development phase.
The economics of testing—test equipment in particular—has received significant attention from many vendors (including ATE manufacturers), customers, and the research community at large. Because of the increasing cost of traditional ATEs, new trends are fast emerging in this area. Features such as multisite organization, architecture modularization, and the increased presence of cheap "testers," such as those included in BIST techniques, are some of the significant developments of recent years. For example, researchers have advocated novel hybrid arrangements (a combination of BIST and ATE) as a possible alternative to speeding up test application time. A substantial departure from past practice is imperative to reduce testing costs and still provide the necessary performance. Future performance, as dictated by the International Technology Roadmap for Semiconductors, must address stringent requirements such as at-speed test and jitter. This will require introducing structural testing as a new class of testing techniques. Today, researchers believe that different approaches and tools will aid in alleviating the increasingly high complexity and cost of testing submicron chips. There is also a pressing decision on a different strategy: The set of tools and tester architectures also require new schemes as test support becomes comprehensive and studies in academia and industry identify new challenges (especially if high speed is a necessity). In this case, the requirements for changing test techniques can vary in the level of cost, complexity, and integration.
Today, testing at Gbps rates is necessary to close the gap between traditional techniques (which rely extensively on ATE) and the technology improvements in ICs and their high clock rate. This requires radical changes in the organization of the test as well as innovative and practical solutions to the support equipment. These changes have a profound impact on many facets of existing test techniques. For example, allowing high transfer rates among channels and functional units (such as in the I/O definition of a SoC) requires readdressing the implication of data format and communication within a serial mode. Moreover, this implies that physical phenomena (such as jitter) are becoming very relevant to tester operation. It is the convergence of all of these issues that makes multigigahertz testing a challenging problem in today's test technology. Here, we provide the readers with a timely account of state-of-the-art research in this area.
The articles in this special issue broadly fall into two parts: The first part includes "Testing Gbps Interfaces without a Gigahertz Tester," by Mak, Tripp, and Meixner; and "Multiplexing ATE Channels for Production Testing at 2.5 Gbps," by Keezer, Minier, and Caron. These articles address novel approaches and frameworks that enable testing of multigigahertz digital devices with or without a modified ATE. In the first article, Mak and his coauthors address in detail the challenges of defining a novel testing problem—namely, at the source synchronous interface. Their technique allows for an order of magnitude increase in data rates while still retaining desirable features, such as low voltages and functional tester accuracy. The proposed technique relies heavily on DFT and, in particular, employs a novel methodology called AC I/O loopback. This technique represents a significant improvement over a simple I/O loopback arrangement: It allows the measurement of multiple functional parameters inclusive of AC timing specifications. The authors outline the application of AC I/O loopback and supporting DFT circuitry for the Intel Pentium 4 processor, showing that their technique can efficiently correlate different stress measurements at the physical layer within a self-test framework. The authors successfully incorporate a combination of timing stress and voltage stress to generate eye diagrams with no need for a high-speed tester.
In the second article, Keezer and his coauthors analyze testing at multigigahertz frequencies using a different technique, namely to multiplex ATE channels for production testing. Several features of current-generation ATE—timing calibration, modularity, temperature effects for sampling logic, and the large number of high channels—all evidence the need for multiplexing. The authors present two versions of multiplexing schemes applicable to ATE. The first scheme uses test resources currently available in an existing ATE, together with new multiplexer circuits to accelerate the speed up to 2.5 Gbps. The scheme uses differential pair signals in a scalable arrangement with embedded ATE circuitry to support accurate timing calibration (albeit jitter makes it prone to timing errors). The second scheme, which is in a prototype stage, addresses the dependency of timing on the ATE, thus reducing the negative influence of jitter on test operations. Moreover, this type of design is expected to ensure high Gbps rates in future systems.
The next two articles deal with a critical measurement issue: jitter. These articles address the modeling aspects of jitter for serial I/O circuits and systems ("Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects," by Ou et al.) and built-in jitter instrumentation ("On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz," by Sunter and Roy). It is well recognized that, because of high operating frequencies, jitter represents a possible source of failure (as well as design malfunction) that test engineers must account for with the utmost care. In the third article, Ou et al. consider jitter as a stochastic process that originates from different sources. Moreover, within a comprehensive model, the authors correlate the effects of jitter to possible failure. In particular, they analyze the bit error rate with respect to the probability density function of the jitter itself (and an associated harmonic oscillator). The investigation extends to a clock recovery circuit and its impact on the overall model: Ou et al. outline an investigation in terms of a framework that enables jitter decomposition and extracts useful information using a very simple analysis. Moreover, Ou et al. show that such modeling becomes a necessity for frequency in the gigahertz ranges, thus establishing a unique approach based on the proposed decomposition.
In the last article, Sunter and Roy further extend jitter analysis to circuitry outside test equipment. Starting with the traditional high-speed sampling oscilloscope technique, the authors review existing measurement schemes such as spectrum and time interval analyzers. They outline advantages and disadvantages with particular emphasis on additional circuitry (such as delay lines) and their influence on the measured jitter. Sunter and Roy propose a frequency-based technique that relies on a novel arrangement that analyzes sample data on-chip at low frequency and shifts the data into a tester for software-based analysis. The technique does not require delay lines or matched oscillators, thus preserving the jitter measurement's accuracy.
We sincerely hope that this special issue will be a reference publication for future research. The topics covered in the articles are timely and important, and the authors have done an excellent job of presenting the material. We extend our sincere thanks to all the authors and reviewers. We also thank Rajesh Gupta, editor in chief of IEEE Design & Test, for allowing us to create this special issue. Finally, a special thanks is due to the editorial staff of the IEEE Computer Society for editing and assembling this issue. Please feel free to contact us if you have questions or comments.