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TABLE OF CONTENTS
Issue No. 03 - May/June (vol. 21)
ISSN: 0740-7475
EIC Message

The next EDA challenge--Design for manufacturability (HTML)

Rajesh Gupta , Editor in Chief, <em>IEEE Design & Test</em>
pp. 169
D&T: 20 Years of Service

1985 to 1987: My years with D&T (HTML)

Vishwani D. Agrawal , Auburn University
pp. 173-174
Panel Summaries

ITC 2003 panels: Part 2 (Abstract)

Fidel Muradali , Agilent Technologies
Geir Eide , Teseda
Mustapha Slamani , IBM Microelectronics
Mike Li , Wavecrest
pp. 175-176, 261-262
Features

Guest Editors' Introduction: Design for Yield and Reliability (HTML)

Philippe Magarshack , STMicroelectronics
Dimitris Gizopoulos , University of Piraeus
Yervant Zorian , Virage Logic
Cary Vandenberg , HPL Technologies
pp. 177-182

Logic Synthesis for Manufacturability (Abstract)

Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley
Alessandra Nardi , University of California, Berkeley
pp. 192-199

Understanding Yield Losses in Logic Circuits (Abstract)

Emil Gizdarski , Synopsys
Alessandra Fudoli , STMicroelectronics
Ben Mathew , Synopsys
Davide Appello , STMicroelectronics
Vincenzo Tancorre , STMicroelectronics
Katia Giarda , STMicroelectronics
pp. 208-215

Defect and Error Tolerance in the Presence of Massive Numbers of Defects (Abstract)

T.M. Mak , Intel
Sandeep K. Gupta , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 216-227

Reconfigurable Architecture for Autonomous Self-Repair (Abstract)

Shu-Yi Yu , Center for Reliable Computing, Stanford University
Nirmal R. Saxena , Center for Reliable Computing, Stanford University
Subhasish Mitra , Center for Reliable Computing, Stanford University
Wei-Je Huang , Center for Reliable Computing, Stanford University
Edward J. McCluskey , Center for Reliable Computing, Stanford University
pp. 228-240

New Challenges in Delay Testing of Nanometer, Multigigahertz Designs (Abstract)

Li-C. Wang , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Angela Krstic , University of California, Santa Barbara
T.M. Mak , Intel
pp. 241-247

DFT for Delay Fault Testing of High-Performance Digital Circuits (Abstract)

Bhaskar Chatterjee , University of Waterloo
Manoj Sachdev , University of Waterloo
Ali Keshavarzi , Intel Laboratories
pp. 248-258
DAC Watch

DAC Highlights (Abstract)

Luciano Lavagno , Cadence Berkeley Labs and Politecnico di Torino
pp. 259-260
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