Issue No. 03 - May/June (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.10
Bhaskar Chatterjee , University of Waterloo
Manoj Sachdev , University of Waterloo
Ali Keshavarzi , Intel Laboratories
Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "DFT for Delay Fault Testing of High-Performance Digital Circuits", IEEE Design & Test of Computers, vol. 21, no. , pp. 248-258, May/June 2004, doi:10.1109/MDT.2004.10