Issue No. 03 - May/June (2004 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.8
Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
T.M. Mak , Intel
As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. This article introduces a new approach for error tolerance resulting in chips containing only errors acceptable for such applications.
T. Mak, S. K. Gupta and M. A. Breuer, "Defect and Error Tolerance in the Presence of Massive Numbers of Defects," in IEEE Design & Test of Computers, vol. 21, no. , pp. 216-227, 2004.