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Issue No. 03 - May/June (2004 vol. 21)
ISSN: 0740-7475
pp: 208-215
Davide Appello , STMicroelectronics
Alessandra Fudoli , STMicroelectronics
Katia Giarda , STMicroelectronics
Vincenzo Tancorre , STMicroelectronics
Emil Gizdarski , Synopsys
Ben Mathew , Synopsys
Yield improvement requires understanding failures and identifying potential sources of yield loss. This article focuses on diagnosing random logic circuits and classifying faults. The authors introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.
Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew, "Understanding Yield Losses in Logic Circuits", IEEE Design & Test of Computers, vol. 21, no. , pp. 208-215, May/June 2004, doi:10.1109/MDT.2004.21
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