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Issue No. 02 - March/April (2004 vol. 21)
ISSN: 0740-7475
pp: 122-131
Prabhat Mishra , University of California, Irvine
Nikil Dutt , University of California, Irvine
Magdy S. Abadir , Motorola
A major challenge in today's functional verification is the lack of a formal specification with which to compare the RTL model. The authors propose a novel top-down verification approach that allows specification of a design above the RTL. From this specification, it is possible to automatically generate assertion models and RTL reference models. The authors also demonstrate that symbolic simulation and equivalence checking can be applied to verify an RTL design against its specification.

P. Mishra, N. Krishnamurthy, M. S. Abadir and N. Dutt, "A Top-Down Methodology for Microprocessor Validation," in IEEE Design & Test of Computers, vol. 21, no. , pp. 122-131, 2004.
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