Issue No. 01 - January/February (2004 vol. 21)
Naran Sirisantana , Intel
Kaushik Roy , Purdue University
<p>Two CMOS design techniques use dual threshold voltages to reduce power consumption while maintaining high performance. Simulation results show power savings of 21% for one technique at low activity, and for the other, 19% at high activity and 38% at low activity.</p>
K. Roy and N. Sirisantana, "Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses," in IEEE Design & Test of Computers, vol. 21, no. , pp. 56-63, 2004.