Issue No. 01 - January/February (2004 vol. 21)
Jinan Lou , Synopsys
Wei Chen , Synopsys
<p>With today's rapidly shrinking process geometries, designers must address crosstalk, electromigration, IR drop, and other effects earlier in the design cycle to achieve signal integrity. The authors present a new placement algorithm that minimizes crosstalk and increases design speed 8% on average, in comparison with a traditional timing-driven, congestion-aware placement flow.</p>
J. Lou and W. Chen, "Crosstalk-Aware Placement," in IEEE Design & Test of Computers, vol. 21, no. , pp. 24-32, 2004.