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Issue No. 01 - January/February (2004 vol. 21)
ISSN: 0740-7475
pp: 24-32
Jinan Lou , Synopsys
Wei Chen , Synopsys
ABSTRACT
<p>With today's rapidly shrinking process geometries, designers must address crosstalk, electromigration, IR drop, and other effects earlier in the design cycle to achieve signal integrity. The authors present a new placement algorithm that minimizes crosstalk and increases design speed 8% on average, in comparison with a traditional timing-driven, congestion-aware placement flow.</p>
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CITATION
Jinan Lou, Wei Chen, "Crosstalk-Aware Placement", IEEE Design & Test of Computers, vol. 21, no. , pp. 24-32, January/February 2004, doi:10.1109/MDT.2004.1261847
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